1. Field of the Invention
The invention relates generally to non-volatile memory devices, and in particular to flash memory cells and manufacturing of flash memory devices.
2. Description of Related Art
Flash memory technology includes memory cells that store charge between the channel and gate of a field effect transistor. The charge stored affects the threshold of the transistor, and the changes in threshold due to the stored charge can be sensed to indicate data.
One type of charge storage memory cell in widespread application is known as a floating gate memory cell. In a floating gate memory cell, a tunnel dielectric is formed over a semiconductor channel, a floating gate of conductive material such as polysilicon is formed over the tunnel dielectric, and an inter-poly dielectric is formed over the floating gate to isolate it from the word line or control gate of the memory cell. A floating gate memory cell is modeled as a first capacitor between the control gate and the floating gate, and a second capacitor between the floating gate and the channel. The coupling ratio is based on the capacitor divider formula that determines the voltage coupled to the floating gate by a voltage applied across the control gate and the channel. Devices are typically made to have a higher capacitance between the control gate and the floating gate than between the floating gate and the channel by engineering the materials and the area of the floating gate relative to the control gate and the channel. For example, floating gates are implemented using a T-shape or a U-shape, which results in a greater surface area between the control gate and the floating gate than between the floating gate and the channel, and thereby a greater capacitance between the floating gate and the control gate. This results in more voltage coupled to the floating gate, enhancement of the electric field across the tunnel oxide, and increased program/erase efficiency. Although this technology has been widely successful, as the sizes of the memory cells and the distances between them shrink, the floating gate technology starts to degrade because of interference between neighboring floating gates.
Another type of memory cell based on storing charge between the channel and gate of a field effect transistor uses a dielectric charge trapping structure. In this type of memory cell, a dielectric charge trapping structure is formed over a tunnel dielectric which isolates the dielectric charge trapping structure from the channel, and a top dielectric layer is formed over the charge trapping structure to isolate it from the word line or gate. A representative device is known as a silicon-oxide-nitride-oxide-silicon SONOS cell. SONOS-type devices, and other charge trapping memory cell technologies that use a non-conductive charge trapping structure, are recently proposed to solve the floating gate interference issue, and they are predicted to perform well below a 45 nm critical dimension, or manufacturing node. However, because the charge trapping layer is not conductive, the series capacitor model of floating gate devices does not apply. Therefore, increasing the area of the control gate and charge trapping structure does not increase a coupling ratio as occurs in a floating gate device. Rather, the electric field when no charge is trapped in the charge trapping structure is equal in the tunneling dielectric and the top dielectric. The program/erase efficiency of a charge trapping memory cell with a dielectric charge trapping structure, like a SONOS-type device, cannot be improved by the coupling ratio engineering known from the floating gate technology.
Therefore, it is desirable to have a dielectric charge trapping memory cell with the electric field strength in the tunneling dielectric greater than the electric field strength in the top dielectric when no charge is trapped in the charge trapping structure for a bias voltage between the channel and the gate, resulting in increased program/erase efficiency.